Company:
Qualcomm Canada ULC
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
QUALCOMM is the world's leading developer of next-generation wireless and multimedia technology.
We are searching for an ASIC design engineer interested in developing world-class solutions for the next generation of AI/ML HW IP.
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Principal Duties:
- Develop of Micro-Architecture and specification based on high level design requirements
- Develop RTL design that meets required performance and is optimized for Area and Power
- Integrate pre-verified sub-IPs to build up larger functionality
- Flow bring up and report analysis for Linting, RTL Synthesis, CLP, CDC
- Work closely with verification team to define testplan, debug regression, analyze coverage reports
- Develop SVA assertions for white box verification for formal verification
- Effective communication across teams, multitasking and well-planned execution of the tasks.
Preferred Qualifications:
- Prior experience delivering Verilog and System Verilog RTL
- Detail oriented with strong analytical and debugging skills
- Strong communication (written and verbal), collaboration, and specification skills
- Practiced design knowledge working with some of the following concepts:
- Clock domain crossing and reset architecture
- Machine Learning HW development
- FIFOs implementation
- Bus implementation/verification techniques
- Memory selection and control
- High speed and low power design optimization
- Bus interface protocols (AHB, AXI)
- Experience with some of the following
- Simulation and code coverage tools (VCS, Verdi, Modeltech/Questa, or Xcelium)
- Design rule and CDC checking (SVA assertions, Spyglass, 0-in, etc.)
- Scripting languages (PERL, Python, TCL, C, etc.)
- Power Intent and Analysis: UPF, CLP, PTPX, PowerPro
- Synthesis: DCG/NXT, FC
- Static Timing: Primetime
- Formal Verification: Conformal, Formality
Minimum Qualifications:
- Legally permitted to work on-site in Canada
- 5+ years of ASIC design, verification, or related work experience.
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