Physical Design Engineer, Sr Lead

Nuvia

Nuvia

Design
Hyderabad, Telangana, India
Posted on Apr 25, 2025

Job Description

Job Posting Date

2025-04-24


Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Preferred Qualifications:

• Bachelors or Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering

• 5+ years of Hardware Engineering or related work experience.
• 1+ year in a technical leadership role with or without direct reports.

Principal Duties and Responsibilities:

  • 5-7 years of relevant experience in ASIC Physical Verification
  • Good understanding of overall design Flow from RTL to GDS.
  • Hands on Experience on Physical Verification closure of full chip & Hierarchical Designs
  • Hands on DRC & LVS Experience on Lower node Technologies with Synopsys/Cadence/Calibre Tools
  • Good knowledge on PnR flow, ECO implementation
  • Knowledge on Perl / TCL scripting language , SVRF coding is advantage
  • Experience on multi voltage designs
  • Good understanding of other domains of signoff of in Physical Design (STA/PV/IR/FV/CLP)

Responsibilities

  • Responsible for Block/ Chip Tile PV closure to achieve the best PPA
  • DRC & LVS closure for Block and Full Chip for complex hierarchical Designs in 4nm/3nm nodes
  • Interaction with IR, IP , ESD & PD teams for Physical Verification Convergence & Resolving Conflicts
  • Able to work on multiple blocks at same time with minimal supervision
  • Responsible for Full Chip LVS & DRC closure
  • Responsible for Analog integration closure for all IP"s used in SOC

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

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If you would like more information about this role, please contact Qualcomm Careers.