Nuvia
General Summary:
We are seeking a highly skilled and motivated Physical Design Engineer to join our team. The ideal candidate will have hands-on experience in RTL-to-GDSII flow, with a strong focus on Floor-planning, Clock Tree Synthesis, Place-n-Route (PnR), DRC and Timing closure. This role involves architecting and implementing robust, low-skew, power-efficient clock distribution networks tailored for a complex design to meet performance, power, and area goals.
This role requires full-time onsite work in San Diego, CA (5 days per week).
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.Key Responsibilities:
Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry-standard tools (e.g., Innovus, ICC2).
Drive timing closure across multiple corners and modes using static timing analysis (STA) tools (e.g., PrimeTime).
Collaborate with RTL designers to resolve timing, congestion, and DRC issues.
Optimize design for power, performance, and area (PPA).
Conduct formal equivalence checks between RTL and netlist.
Support physical verification including DRC, LVS, and antenna checks.
Work closely with backend teams for tapeout preparation and signoff.
Excellent scripting skills (TCL, Python, Perl) for reference flow automation.
Execute full-chip and block-level physical verification including DRC, LVS, ERC, antenna, and density checks using industry-standard tools (e.g., Calibre, Pegasus, ICV).
Customize and optimize reference physical verification flows to align with project needs and foundry requirements.
Perform GDS-to-GDS comparisons to validate ECO changes, ensure layout integrity, and support tapeout readiness.
Debug and resolve physical verification violations, working closely with layout, design, and CAD teams.
Collaborate with foundries to ensure compliance with latest design rule manuals (DRMs) and tapeout checklists.
Support signoff verification, including multi-corner/multi-mode analysis and ECO validation.
Develop and maintain automation scripts for verification flows, reporting, and regression testing.
Interface with EDA vendors to resolve tool issues and improve flow robustness.
Participate in design reviews, providing feedback on layout quality, rule compliance, and manufacturability.
Ensure timely delivery of clean GDSII for tapeout, with full verification signoff.
Perform full-chip and block-level static timing analysis (STA) using industry-standard tools (e.g., Synopsys PrimeTime, Cadence Tempus).
Develop, validate, and maintain timing constraints (SDC) for multiple modes and corners.
Collaborate with RTL, synthesis, and physical design teams to ensure timing-aware design practices.
Debug and resolve setup, hold, and transition violations across various PVT corners.
Drive timing closure through iterative optimization and ECO implementation.
Customize and enhance timing analysis flows to improve accuracy, efficiency, and scalability.
Analyze clock tree timing, including skew, latency, and jitter impacts.
Support signoff timing verification, including cross-domain timing and false/multicycle path handling.
Interface with EDA vendors to resolve tool issues and improve flow robustness.
Participate in design reviews, providing insights on timing risks and mitigation strategies.
Define and implement low-power architecture using CLP methodology across RTL and physical design stages.
Develop and maintain power intent files (UPF/CPF) and ensure alignment with design specifications.
Customize and optimize low-power reference flows to meet project-specific requirements.
Collaborate with RTL, synthesis, and physical design teams to integrate power-aware features such as power gating, retention, isolation, and level shifting.
Perform power-aware static checks, simulation, and formal verification to validate power intent.
Debug and resolve issues related to power domain crossings, voltage islands, and power sequencing.
Support signoff verification including power-aware LVS/DRC, STA, and EM/IR analysis.
Interface with EDA vendors to resolve tool issues and improve low-power flow robustness.
Participate in design reviews, providing insights on power architecture, risks, and mitigation strategies.
Ensure compliance with foundry low-power guidelines and contribute to successful tapeout.
Qualifications:
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
4+ years of experience in physical design, with a focus on clock tree design and implementation.
Strong understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design.
Proficiency with EDA tools for CTS, STA, and physical verification (e.g., ICC2, Innovus, PrimeTime).
Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies.
Solid scripting skills (TCL, Python, Perl) for flow automation and data analysis.
Familiarity with low-power design techniques, including clock gating and multi-voltage domains.
Preferred Skills:
Experience with custom clock tree architectures such as H-tree, mesh, or spine-based topologies.
Knowledge of EM/IR analysis, thermal-aware clocking, and reliability modeling.
Exposure to high-speed interface clocking (e.g., SerDes, DDR, PCIe).
Understanding of package-level clock planning and signal integrity.
Principal Duties & Responsibilities:
• Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.
• Creates advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.
• Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs.
• Evaluates all aspects of complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.
• Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages.
• Writes and reviews detailed technical documentation for complex EDA/IP/ASIC projects.
Level of Responsibility:
• Works independently with minimal supervision.
• Provides supervision/guidance to other team members.
• Decision-making is significant in nature and affects work beyond immediate work group.
• Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc.
• Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions).
• Tasks do not have defined steps; planning, problem-solving, and prioritization must occur to complete the tasks effectively.
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Pay range and Other Compensation & Benefits:
$140,000.00 - $210,000.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.