Advanced Nodes Digital Yield Diagnostics Engineer

Nuvia

Nuvia

Hsinchu City, Taiwan 300
Posted on Dec 5, 2025


Company:

Qualcomm Semiconductor Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Job Summary:
We are seeking a highly motivated and detail-oriented engineer to join our team as a Digital Yield Diagnostics Staff Engineer. In this role, you will be responsible for analyzing and improving the yield performance of digital semiconductor products through data-driven diagnostics and cross-functional collaboration. The ideal candidate will have a strong academic background (M.S. or Ph.D.) and hands-on experience in semiconductor yield analysis, failure diagnostics, and data mining. You will work closely with design, test, process, and quality teams to identify yield limiters and drive continuous improvement.

Key Responsibilities:

  • Perform yield and diagnostics analysis for digital products across various manufacturing stages (wafer sort, final test, etc.).
  • Identify and investigate yield loss failure mechanisms using statistical tools, scan diagnosis, and electrical failure data.
  • Collaborate with foundries, test engineers, and design teams to drive root cause analysis and corrective actions.
  • Monitor yield trends and develop dashboards or reports to track key performance indicators.
  • Work new product introduction (NPI) by providing yield risk assessments and early-stage data analysis.
  • Utilize scan diagnosis and pattern analysis to interpret digital failure signatures and guide debug efforts.
  • Develop predictive yield models to forecast yield of future products for business planning and supply chain decisions.

Qualifications:

  • Hands-on experience with advanced technology nodes (3nm, 2nm) in semiconductor manufacturing and yield improvement.
  • Experience in digital yield analysis, scan diagnosis, or failure analysis in the semiconductor industry.
  • Familiarity with digital design architecture and testing methodologies.
  • M.S. or Ph.D. in Electrical Engineering, Semiconductor Physics, or a related field.
  • Proficiency in data analysis tools such as JMP, Yield Explorer, Python, Excel, Power BI.
  • Strong problem-solving skills and ability to work in a cross-functional environment.
  • Good communication skills in English

Preferred Qualifications:

  • Experience with scan diagnosis tools and techniques (e.g., Yield Explorer).
  • Familiarity with advanced semiconductor process flow, PCM, and inline metrology.
  • Experience working with foundry and backend teams on digital yield improvement.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

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