Nuvia
General Summary:
Qualcomm France-QITC develop interconnect for complex SoCs providing low power, higher system bandwidth, greater IP flexibility, fewer global wires and easier timing convergence as well as faster time to market than existing bus interconnects. QITC NoC solution includes a full suite of automated NoC Design Tools that improve designer productivity.
The engineer will implement system level platforms based on Qualcomm IPs targeting FPGA Emulation or RTL simulation. These platforms will be delivered to validation team, which will conduct CPU to DDR functional verification and performance analysis of Snapdragon IPs and Chips.
Responsibilities:
The engineer will be responsible for building and maintaining system level platforms for RTL simulation and FPGA Emulation. It includes the integration in systemVerilog of Snapdragon IPs such as CPUs, SMMU, interconnects or memory controllers. He will have to provide functional platforms to validation team by running and debugging integration and system level testcases. The engineer will implement system platforms on various Emulators. He may participate in designing RTL modules for the testbench such as traffic generators or DDR memory models coding in systemVerilog or C language (DPI-C).
Skills and Experience:
Good RTL development skills: SystemVerilog/Verilog integration and design. RTL Simulation. debugging
Systems understanding: Bus Protocols, DDR, SOC.
Emulation methodologies knowledge
Additional Skills:
Python, C, C++
Strong motivation and team spirit
Working environment: Linux, ModelSim
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field.*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
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