Company:
Qualcomm India Private Limited
Job Area:
Engineering Group, Engineering Group > Software Engineering
General Summary:
Role Summary
- We are seeking a hands-on, domain-strong engineer to architect, build, and optimize embedded platforms on Zephyr OS with deep ownership of low‑power strategies.
- The role encompasses activities around end-to-end system power – with specific focus on leading power optimization and debug in Software.
- The role expects co-working with cross‑functional teams (sensors, display, connectivity, product SW) to generate comprehensive reports and presentations summarizing analysis results and providing actionable recommendations to cross-functional teams
Minimum Qualifications:
• Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Software Engineering or related work experience.
OR
Master's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience.
OR
PhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience.
• 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc.
Preferred Qualifications:
• Master's/bachelor's Degree in Engineering, Information Systems, Computer Science or related field.
• 6 to 8 years of Software Engineering or related work experience.
Principal Duties and Responsibilities:
Must-Have Skills
- Demonstrated expertise in C/C++ programming, with proven ability to write efficient code for low-power, memory-constrained embedded systems. Compiler optimizations for size and speed.
- Hands-on experience in RTOS-based environments; exposure to Zephyr/FreeRTOS is a must. Familiarity with RTOS power management frameworks (e.g., Zephyr PM APIs, FreeRTOS tickless idle). Expertise in interrupt handling and wake-up sources analysis, Peripheral power gating and dynamic frequency scaling (DVFS).
- Proven experience in implementing advanced low-power use cases and integrating complex display and sensor solutions for smartwatch platforms (thorough understanding of deep sleep modes, and wake-source handling)
- In-depth knowledge of ARM architecture, Ability to read through/investigate complex SOC designs
- Proficiency with power analyzers, oscilloscopes with current probes, and tools like Otii Arc, Keysight N6705
- Proficiency with reading of data sheets, understanding schematics, Power trace tools
- Excellent communication skills, with the ability to author and review detailed design documentation for complex features and interfaces. Or drive multi team debugs.Experience in Mentoring junior engineers; lead small feature squads and cross‑team task forces
Desirable Skills
- Experience in developing and utilizing performance and power models using languages such as C and Python
- Understanding of SoC architecture, PMIC design, and interconnect power domains.
- Familiarity with PMIC telemetry and GPIO state dump tools for real-time power tracking. Ability to correlate current consumption profiles with code execution using trace markers
- Skills in DOU (Days of Use) modeling based on system sleep/wake patterns. Understanding of battery discharge curves, SOC (State of Charge), and dynamic load simulation.
- Knowledge retention modes for ITCM/DTCM banks, Familiarity with power sequencing and corner voting mechanisms.
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