Company:
Qualcomm India Private Limited
Job Area:
Engineering Group, Engineering Group > Hardware Engineering
General Summary:
Job Overview
- Candidate will be responsible for next generation WLAN hardmacro implementation
- The candidate will work with best-in-class methodologies, tools and technology to design innovative WLAN products at the block/IP-level and at system-level in 6nm and beyond (process technologies).
- This role will require the candidate to work on physical and power aware synthesis, logic equivalence, constraints generation & validation, static timing analysis
- Optimize data path design for low-area, low-power and high-speed using advanced features in synthesis such as MCMM, SAIF, multibit mapping etc.
- You will be working with physical design team (and other teams) on timing closure, CAD teams, IP teams and Design Technology Teams for flow scripts/tools development and validation.
- Should be able to work on netlist level ECOs manually or with conformal ECO tool.
- The candidate should also possess automation skills and be well versed in scripting languages
- The candidate should be able to mentor junior members of the team.
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
Minimum Qualifications
- Bachelor’s or Master’s in Electrical Engineering or related field
- 3 to 5 years of experience in SOC logic synthesis and timing constraints
Preferred Qualifications
- Must hold a Bachelor’s and/or a Master’s in Electrical Engineering with at least 3 to 5 years’ experience in SOC logic synthesis and timing constraints
- Experience required in one or more tools/areas: Synthesis (DCG/FC/Genus), Formal Verification (LEC/Formality), STA (Primetime)
- Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling.
- Hands-on experience with STA tools - Prime-time, Tempus
- Have experience working on timing convergence at Chip-level and Hard-Macro level.
- Good understanding of timing constraints development
- Good understanding low power and power simulations using ptpx/power artist/conformal low power
- Could be substituted for experience in Physical Design or Circuit Design, with eagerness to learn front-end implementation tool flows
- Should have good analytical ability, problem solving skills and be a self-starter
- Candidate should be able to lead and work in a team environment
- Good scripting skills using tcl/perl languages
· Strong communication skills to work with design teams worldwide
· Familiarity with the following is a plus, but not required : Digital Communications, LTE/802.11 protocols
Keywords
Synthesis, Implementation , ASIC, STA, PD, Formal Verification, UPF, CLP, Primetime, Backend
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