Nuvia
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.Summary of Responsibilities: This FTE replacement is vital for characterizing PLLs in SerDes and DDR PHYs. With the upcoming roadmap moving to higher and higher speeds, it increases the complexity of HSIO/DDR characterization. This resource will ensure SerDes PLL IP robustness, allowing other engineers to focus on SerDes specific IP char and compliance characterization—boosting efficiency and delivery quality. This resource will in support Short-term: Bonsai, Hawi, Shikra Long-term: Trenton, Tinago, Honu, Triberg Key Responsibilities: Optimize SerDes PLL analog settings for stability across voltage and temperature corners Debug and resolve design, process, platform, and software issues in SerDes PLL and interfaces Enable scalable, cost-efficient ATE coverage for production testing
Role title not 1 level down justification: The requested title is Engineer. One level down engineer will not be having the skillsets to start immediately with the PLL char tasks. It will need significant training to ramp up the one level down engineer, Hence this position will require Engineer title
Justification: The current HSIO team is already fully loaded across multiple PHY IPs (PCIe, USB, CSI, DSI, etc.) and overlapping projects. Existing engineers cannot absorb PLL char responsibilities without compromising deliverables on other critical IPs. With a tightly packed roadmap and increasing PHY complexity, the SerDes PLL a critical IP and requires a dedicated resource to debug, analyze, and resolve silicon issues. This is essential to ensure timely delivery of high-quality parts and software to customers.
Business Impact: Products across XR, Wearables, IIOT, and Compute rely heavily on SerDes and DDR interfaces. As roadmap speeds increase, so does the complexity of HSIO/DDR PHY characterization. The SerDes PLL is a critical IP block, and its robust characterization is essential to ensure high-quality silicon and software delivery. This FTE replacement enables execution of HSIO/DDR char catering to growth BU products for QCOM. Impact if Not Approved: In the short term, SerDes SW quality for platforms like Mahua, Balsam, Molokai, Hawi, and Alana will be compromised. Long-term consequences include delays in IP settings deliverables for Shikra, Trenton, Tinago and Triberg.
Altnernatives Considered: The requested backfills is essential to maintain full operational capacity and preserve critical expertise aligned with our roadmap diversification strategy. This follows a comprehensive evaluation of alternatives, including role consolidation, reallocation of REQs to diversification-priority groups, and leveraging efficiency gains from prior projects.
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