Nuvia
General Summary:
Qualcomm France (QITC Qualcomm Interconnect Technology Center) division develops and deploys custom-built interconnect (NoC – Network-on-Chip) hardware IPs, software tools, exploration and verification methodologies so that SoC integration teams can quickly assemble SoCs with the desired Power Performance Area (PPA) characteristics.
To this end, QITC technology embraces the complete SoC infrastructure to provide increased SoC performance at minimal cost for integration. Our work is at the backbone of the SoC, interconnecting all major IP solutions. You will join a team of talented engineers that creates and implements solutions aiming at increasing the division’s productivity mainly through automation.
According to the missions, the team takes actions at various stages of the product’s development cycle. The team is also involved in enabling new technologies required by next generation products. The engineer would be responsible of various missions aiming at automating NoC components deployment in order to enrich our tool suite.
This is a challenging position, working on most innovative technologies, surrounded by experts and interacting with other teams according to the missions.
Missions include: - writing C++ libraries to emulate components (randomized but valuable traffic generation, eg. AMBA CHI) - writing C++ libraries such as protocol checkers or other generic problem-solving libs - writing Python components and scripts to automate and instrument the flow
And if desired, also: - take part in the continuous enhancement of the current tool chain (Python, Bash, third-party tools, eg. from Cadence and Synopsys) - participate to the creation of a web platform (Docker, Kubernetes, VueJS, MongoDB) Skills and Experience: C++ (good) Python (average) Shell scripting, command line (average) Git Mathematics background.
Optional skills: Hardware RTL design and/or verification methods (SystemVerilog, VHDL, SystemC, test benches, EDA tools: Cadence XCelium and JasperGold, Synopsys VCS). Cache coherency knowledge. Understanding of hardware communication protocols (AXI, ACE, AHB, CHI, …) C++ tools: Clang, GCC, GDB, linters
Educational Requirements: Engineering degree / MsC degree and above in computer science, micro-electronics or similar field.
All experience levels are welcome to apply but preference for Engineers with 7+ years experience
Location: We are open on the location being based in our Sophia Antipolis or Guyancourt office.
Friendly working environment is part of Qualcomm's culture. Additionally, you will enjoy:
Keywords: SoC, ASIC, Interconnect, Cache, CPU, GPU, Coherency, C++, python, algorithm, debug, verification
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
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