Company:
Qualcomm Semiconductor Limited
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
Location: Hsinchu, Taiwan (Onsite, 5 days/week)
Must have keywords: 3DIC, Yield Analytics, DRAM
Nice to have keywords: Diagnostics, ML/AI
We are seeking a highly skilled Diagnostics Analytics Engineer to advance data-driven yield learning for advanced 2.5D and 3DIC products. The role involves interpreting a wide range of diagnostic data, including memory bitmaps, scan diagnosis results, TSV and interposer test outputs, and packaging-related failure signatures, to identify patterns and pinpoint likely root causes. A key responsibility is integrating heterogeneous 3DIC test data across wafer, module, and stacked configurations to build clear, actionable insights that guide yield improvement. Experience applying AI-assisted analysis and solutions is a plus.
Key Responsibilities:
Diagnostics Data Analysis
- Analyze large-scale fail data from wafer sort, final test, and module/stack testing to identify systematic and parametric failure trends.
- Interpret memory bitmap diagnostic data across SRAM, embedded DRAM, and stacked DRAM; classify fail modes and correlate with known defect signatures.
- Evaluate TSV/interposer failures, continuity test results, and 3D stack test patterns to detect systematic issues across layers.
- Analyze scan and ATPG diagnosis output, perform clustering of suspected root causes, and support defect mechanism narrowing.
Yield Learning & Correlation
- Correlate diagnostic results with layout, process, fab metadata, packaging steps, and environmental stress factors.
- Identify high-impact failure mechanisms and quantify their impact on yield, DPPM, and reliability.
- Build structured workflows for correlating memory repair data, redundancy usage patterns, and defect densities across multiple lots or product families.
- Provide clear summaries that accelerate root-cause identification for silicon, assembly, and test teams.
Workflow, Tooling, and Automation
- Develop and maintain scripts, dashboards, or utilities to automate analysis of diagnostic results.
- Work closely with internal software teams to improve data pipelines for memory bitmaps, scan diagnosis, and 3DIC test logs.
- Use statistical techniques and selective AI/ML methods where they enhance signal extraction, clustering, or anomaly detection.
- Ensure analysis workflows scale across product ramps and large data volumes.
Cross-Functional Collaboration
- Partner with test engineering, DFT, process technology, packaging, and FA teams to interpret diagnostic data and validate hypotheses.
- Deliver clear visualizations and reports to guide decision-making for yield improvement.
- Participate in cross-functional deep dives on systematic failure mechanisms and propose data-supported next steps.
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Preferred Qualifications:
- Master’s or Ph.D. in Electrical Engineering, Computer Engineering, Data Science, or related field.
- Extensive experience in yield analysis, including advanced 2.5D, 3DIC, and DRAM products.
- Strong understanding of semiconductor test results analysis, silicon debug, or memory diagnostics, and scan diagnostics.
- Proficiency in Python or equivalent languages for data analysis and automation.
- Ability to interpret complex test datasets and extract meaningful diagnostic signals.
- Strong English communication skills with ability to present technical conclusions clearly.
Preferred Skills:
- Experience with memory bitmap analysis, memory fail-mode classification, and BIST/BIRA repair data interpretation.
- Familiarity with layout correlation workflows and root-cause narrowing using design/process metadata.
- Understanding of TSV/interposer failure signatures and 3DIC test flows.
- Ability to apply statistical techniques or light ML methods for clustering or anomaly detection.
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