Nuvia
General Summary:
Join our team building next-generation CPU verification solutions for cutting-edge RISC-V processors.
Location: Bangalore , Santa-Clara.
What You’ll Do:
Design and implement a configurable instruction generator for RISC-V ISA.
Enable automated test generation for functional and microarchitectural coverage.
Support custom ISA extensions and advanced features.
Integrate with simulation/emulation environments for high-performance verification.
What We’re Looking For:
Strong understanding of RISC-V architecture and ISA.
Proficiency in Python/C++ (bonus: experience with DSLs or generator frameworks).
Familiarity with verification flows, random instruction generation, and coverage-driven methodologies.
Passion for open-source and CPU design innovation.
Why Join Us?
Work on open standards and contribute to the RISC-V ecosystem.
Collaborate with world-class architects and verification engineers.
Opportunity to innovate and influence verification strategies for complex SoCs.
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
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