Nuvia
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.As a Lead / Staff / Senior Staff Physical Design Engineer in the GPU team, you will be responsible for the end‑to‑end physical implementation of high‑performance, low‑power GPU cores used across mobile, compute, and automotive platforms. You will work closely with RTL, micro‑architecture, DFT, STA, and signoff teams to deliver best‑in‑class PPA (Performance, Power, Area) on advanced technology nodes.
Staff and Senior Staff engineers are expected to drive block‑level ownership, make critical PPA trade‑offs, mentor junior engineers, and influence physical design methodology, while Lead engineers focus on strong technical execution and convergence.
Own complete Physical Design / Physical Implementation flow for complex GPU cores, including:
Floorplanning
Place and Route
Clock Tree Synthesis (CTS)
Static Timing Analysis (STA)
Physical Verification (DRC/LVS)
Formal verification
Power Delivery Network (PDN) design
Drive timing closure for high‑frequency, data‑path‑intensive GPU blocks across multi‑mode, multi‑corner scenarios
Optimize PPA trade‑offs and push designs to aggressive performance and power targets on advanced technology nodes
Perform timing ECOs, functional ECO roll‑ins, and debug critical timing, power, and physical violations
Collaborate closely with RTL, micro‑architecture, DFT, and signoff teams to resolve constraints, clocking, and implementation issues
Develop and apply low‑power implementation techniques and customized P&R strategies for GPU cores
Contribute to PD flow automation, methodology improvements, and efficiency enhancements using scripting
Mentor junior engineers and provide technical leadership (Staff / Senior Staff levels)
Required Technical Skills
6 to 15 years of experience in Physical Design / Physical Implementation for complex SoCs or high‑performance cores (GPU or CPU preferred)
Strong hands‑on experience with industry‑standard P&R tools such as Synopsys ICC2 and/or Cadence Innovus
Strong expertise in Static Timing Analysis using PrimeTime and/or Tempus
Deep understanding of advanced STA concepts and clocking architecture
Experience with multi‑corner timing closure and high‑frequency designs
Solid understanding of PDN design, power optimization, and leakage control
Proficiency in Tcl and/or Perl scripting for flow automation
Experience working on advanced deep sub‑micron technology nodes
Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
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