Nuvia
General Summary:
The Senior Staff Engineer leads a small team of Staff Engineers responsible for enabling customers to successfully use and integrate all IP on the SoC. The role is documentation-first, with a heavy emphasis on authoring and scaling silicon Technical Reference Manuals (TRMs) and associated customer-facing collateral, and expands into customer applications support as programs ramp. The Senior Staff Engineer owns the team’s deliverables end-to-end, drives planning/execution, ensures quality and on-time delivery, and serves as the technical decision-maker and primary point-of-contact for the SoC enablement documentation program.
Team & Scope
Leads 4 Senior Engineers executing SoC-wide TRM creation and customer enablement workstreams (covering clocks/resets/buses/IO/error events/interrupts and IP programming guidance across the SoC).
Owns a delegated area of responsibility and is accountable for the team’s overall delivery (not just individual tasks).
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.Key Responsibilities
1) Program & Delivery Ownership (Team Lead)
Owns the SoC TRM execution plan: scope, task breakdown, assignments, scheduling, and delivery readiness across the team.
Drives milestone-based execution for TRM phases (e.g., Phase drafts, review cycles, and publication handoffs), ensuring dependencies are identified and actively managed.
Tracks execution and quality metrics for the TRM program and ensures organizational goals are met (schedule, completeness, review closure, publication readiness).
2) Technical Leadership for Silicon TRMs (SoC-wide IP Enablement)
Establishes and enforces technical standards for TRM content quality, consistency, and “customer-appropriate” exposure (filtering internal-only information and aligning diagrams/nomenclature to external-friendly standards).
Leads cross-functional content harvesting and consolidation:
Gathering inputs from Hardware Programming Guides (HPG), Hardware Design Guides (HDD), Hardware Settings References, internal SoC repositories (clocks/resets/buses/IO/error events/interrupts), and relevant third-party IP documentation with SoC parameterization notes.
Ensures high-value usability features are built into the TRM deliverables where applicable (e.g., programmer sequences with register references, validation checks that references map to correct register listings).
3) Review Governance & Publication Readiness
Runs the technical review mechanism: coordinates with IP SMEs, drives closure of review feedback, and ensures the team delivers high-quality “ready-to-publish” drafts to Tech Comm / publishing stakeholders.
Owns the team’s quality bar and takes responsibility for deliverable integrity, completeness, and correctness (including addressing gaps or conflicting inputs).
4) Vendor / Partner Execution (if applicable to the program model)
Leads execution coordination across internal and external contributors consistent with the TRM program workflow (e.g., QC tech lead/IP engineer inputs, external authoring to TRM standards, diagram redaction/redraw, nomenclature normalization).
Ensures handoffs are crisp: what the team must provide (source assets, internal content, register listings), what external partners produce (drafts, rewrites, diagram updates), and how review/publish gates are satisfied.
5) Escalation Handling & Customer Enablement Support (as the team ramps)
Acts as the escalation point for complex customer enablement issues that require deep system knowledge, debugging expertise, or cross-team alignment.
Guides the team’s progression from documentation-first into broader customer application support responsibilities, minimizing context-switching while building a scalable support model.
Lead Applications Engineer (Hardware‑focused) — Qualifications
Minimum Qualifications
Experience required: 8 to 17 years
Bachelor’s degree in Engineering (EE/CE preferred) or related field (or equivalent practical experience).
Proven ability to lead complex customer issues end-to-end: triage, debug strategy, root cause isolation, cross-team coordination, and closure.
Demonstrated experience providing technical expertise through customer engagements such as product demonstrations, solution integration, and sustaining support.
Experience partnering with sales/product/business teams to assess solution fit, shape requirements, and translate customer needs into actionable engineering plans.
Strong technical communication skills: can explain complex hardware topics clearly to mixed audiences and influence decisions when tradeoffs are required.
Strong ownership and prioritization across multiple programs/customers with minimal supervision.
Preferred Qualifications
Experience acting as the technical point-of-contact for major accounts or key programs.
Experience mentoring or guiding other applications engineers (debug methodology, best practices, documentation quality).
Track record of creating scalable enablement assets (debug playbooks, hardware checklists, known-issues guidance) that reduce repeat escalations.
Broad hardware platform exposure (board bring-up, power/perf/thermal considerations, compliance considerations depending on domain).
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